This invention relates to the packaging of power semiconductor devices in both single chip and multiple chip packages, with enhanced electrical and thermal characteristics.
One approach to packaging power semiconductor devices is shown in Fillion et al U.S. Pat. No. 5,637,922, wherein power semiconductor devices are mounted to a direct bond substrate, and high density interconnect (HDI) techniques are employed to form electrical connections to device top contact pads, using relatively thick copper metallization. The structures of Pat. No. 5,637,922 have the advantages of excellent thermal conductivity for carrying heat away from the bottom of the semiconductor device, the elimination of electrical parasites which would otherwise be caused by wire bond connections, reliability and robustness. Cost however is a factor, as well as the inability to mix devices of different thicknesses. In addition, it is desirable to provide semiconductor device packages which are flat on both sides, to facilitate the attachment of heat sink structures to both sides.